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Viewing: ECE 6250 : ASIC Design and Testing of VLSI Circuits

Last approved: Sat, 17 Dec 2016 09:03:27 GMT

Last edit: Mon, 21 Nov 2016 00:03:12 GMT

Other Courses referencing this course
School of Engineering and Applied Sciences
Electrical and Computer Engineering (ECE)
ECE
6250
ASIC Design and Testing of VLSI Circuits
ASIC/Design/Testing VLSI
Spring 2017
0,3
Course Type
Laboratory
Lecture
Default Grading Method
Letter Grade

No
No
ECE 4140 or ECE 6240
Corequisites

20

Frequency of Offering
Every Year
Term(s) Offered
Spring
Are there Course Equivalents?
Yes
 
ECE 4150 - ASIC Design and Testing of VLSI Circuits
No
Fee Type


No


ASIC and mixed-signal design methodology, use of ASIC design CAD tools; logic synthesis, styles of synthesis, power/area/speed constraints; MIPS CPU HDL implementation/verification/testing; VLSI testing, fault models, design for testability techniques, scan path, built-in self-test. Chips designed and fabricated in ECE 4140 or ECE 6240 or equivalent course are tested.
As a result of completing this course, students will be able to:
1. Conduct modeling and simulation of digital system using hardware description language (HDL)
2. Design and implement MIPS CPU Architecture
3. Create a Synthesis of digital controller/system from register-transfer to higher level descriptions in HDL
4. Explain the concept of design for test, fault modeling, ATPG, BIST and IDDQ measuring,
5. Describe methodologies in ASIC design flows included DFT,
6. Test the ASIC chip by using Logic Analyzer.
Uploaded a Course Syllabus

Course Attribute


Key: 9841