Preview Workflow

The CIM Courses system will be down temporarily undergoing routine maintenance.

Viewing: ECE 6214 : High-Level VLSI Design Methodology

Last approved: Wed, 22 Feb 2017 09:01:45 GMT

Last edit: Mon, 06 Feb 2017 16:45:33 GMT

School of Engineering and Applied Sciences
Electrical and Computer Engineering (ECE)
ECE
6214
High-Level VLSI Design Methodology
VLSI Design
Fall 2017
3
Course Type
Lecture
Default Grading Method
Letter Grade

No
No
ECE 6213
Corequisites

20

Frequency of Offering
Every Year
Term(s) Offered
Spring
Are there Course Equivalents?
No
 
No
Fee Type


No


High-level ASIC–FPGA design methodology. RTL modeling of VLSI circuits, using HDL for synthesis. Detailed discussion of logic synthesis. Architectural tradeoff for large VLSI circuits. Advanced optimization techniques. VLSI design flow, using the state-of-the-art, front-end design entry and simulation tools and back-end logic synthesis.
After completing the course, the student will be able to do:
• Modeling and simulation of digital system using hardware description language (HDL),
• Explain the concept of ASIC design back-end process and FPGA debug and implementation,
• Explain the concept of state-of-the-art low power design methodology for ASIC, FPGA, and mobile system,
• Design/simulation/synthesis/implementation of a multi-core process architecture,
• Design and implement the DSP design concept for wireless communication and target to ASIC and FGPA demo board (Altera),
• Debug and analysis a system with an on-board logic analyzer, and explain the advance low power design flow for a mobile device.
Uploaded a Course Syllabus

Course Attribute


Key: 2447