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Viewing: ECE 4150 : ASIC Design and Testing of VLSI Circuits

Last approved: Fri, 10 Jun 2016 08:03:28 GMT

Last edit: Thu, 09 Jun 2016 16:48:14 GMT

Programs referencing this course
Other Courses referencing this course
School of Engineering and Applied Sciences
Electrical and Computer Engineering (ECE)
ECE
4150
ASIC Design and Testing of VLSI Circuits
ASIC/Design/Testing VLSI
Summer 2015
0,3
Course Type
Laboratory
Lecture
Default Grading Method
Letter Grade

No
Yes
ECE 6250 - ASIC Design and Testing of VLSI Circuits
ECE 4140
Corequisites

20

Frequency of Offering
Every Year
Term(s) Offered
Spring
Are there Course Equivalents?
Yes
 
ECE 6250 - ASIC Design and Testing of VLSI Circuits
No
Fee Type


No


ASIC and mixed-signal design methodology, use of ASIC design CAD tools. Logic synthesis, styles of synthesis, power/area/speed constraints. MIPS CPU HDL implementation/verification/testing. VLSI testing, fault models, design for testability techniques, scan path, built-in self-test. Testing of chips designed and fabricated in ECE 4140 or equivalent chips.
This course provides a top-down ASIC mixed-signal design methodology, used of ASIC design CAD tools. VLSI testing, fault models, design for testability techniques, scan path, built-in self-test. After completing the course, the student will be able to: modeling and simulation of digital system using hardware description language (HDL), design and implement MIPS CPU Architecture, synthesis of digital controller/system from register-transfer to higher level descriptions in HDL, explain the concept of design for test, fault modeling, ATPG, BIST and IDDQ measuring, describe methodologies in ASIC design flows included DFT, test the ASIC chip by using Logic Analyzer.
Uploaded a Course Syllabus

Course Attribute
CCAS - Professional

Key: 2269